Technical Field
The present disclosure relates to a display device having an array substrate and a method of manufacturing the same, and more specifically to an array substrate capable of reducing signal delay in clock signal lines and reducing the size of a bezel in a non-display area.
Description of the Related Art
As the era of information technology has begun, the field of display that represents electrical information signals graphically has been rapidly growing. In accordance with this, various display devices which are thinner, lighter and consume less power have been developed.
Examples of such display devices include a liquid crystal display (LCD) device, a plasma display panel (PDP) device, a field emission display (FED) device, and an organic light emitting display (OLED) device, etc.
Among these, LCD devices are most broadly employed as display devices for mobile devices in place of cathode ray tube (CRT) devices since LCD devices exhibit good quality, are light and thin and consume less power. In addition to mobile applications such as monitors of laptop computers, LCD devices are being developed for various applications such as televisions, monitors of computers, etc.
An LCD device includes a color filter array substrate on which color filters are formed, a thin-film transistor array substrate on which thin-film transistors are formed, and a liquid-crystal layer formed between the color filter array substrate and the thin-film transistor array substrate.
Among LCD devices of a variety of liquid-crystal modes, a LCD device employing horizontal electric field technology drives a liquid-crystal layer by in-plane-switching (IPS) manner by generating electric field between a pixel electrode and a common electrode disposed in parallel with a lower substrate. Such IPS-LCD devices have the advantage of wide viewing angle but have the drawback of low aperture ratio and low transmittance.
To overcome such drawbacks of IPS-LCD devices, a FFS (fringe field switching)-LCD device driven by fringe field has been proposed.
A FFS-LCD device includes a common electrode and a pixel electrode with an insulation layer therebetween in every pixel area, and fringe field in the form of an arc is generated above the common electrode and the pixel electrode. As liquid-crystal molecules disposed between upper and lower substrates are aligned by the fringe field, the aperture ratio and transmittance can be improved compared to IPS-LCD devices.
Recently, as well as requirements for light and thin display device, in order to meet the requirement for slim design of end-products such as monitors or televisions, a display device having a narrow bezel, i.e., reduced width of the non-display area surrounding the display area, especially reduced left and right bezel is in demand.
To implement such narrow bezel, the technique is employed that forms thin-film transistors (TFT) for driving pixels on the lower substrate (TFT array substrate) of an LCD device by using amorphous silicon (a-Si) and integrates a gate-in-panel (GIP) circuit working as a gate shift register into the lower array substrate of the liquid-crystal panel.
The GIP circuit is a kind of shift register and is operated sequentially by receiving clock signals via clock signal lines (CLK lines). The clock signal lines are responsible for inputting GIP signals. Delay in the input signals has to be small so as to reduce delay in output signals. If the delay in the signals increases with the load on the clock signal lines, the lifespan of the GIP circuit and the size of a buffer, i.e., a transistor included in the GIP circuit may be affected.
The RC delay in the clock signal lines may appear depending on a resistance component R and a capacitance component C. The resistance component R may be associated with the line width of the clock signal lines. The capacitance component C may be associated with capacitance between overlapping clock signal lines, and parasitic capacitance of transistors TRs using the clock signal lines.
The present inventors have recognized that in existing array substrates, in order to reduce resistance, a plurality of clock signal lines having a small line width could be arranged in the horizontal direction. In this manner, however, the size of the bezel undesirably increases. Further, overlap capacitance between the clock signal lines and between clock signal lines and connection lines connecting the clock signal lines to the GIP circuit is undesirably increased. Therefore, RC delay may not be sufficiently reduced at the cost of increased bezel.
Moreover, as the size of the bezel should be reduced in order to implement LCD devices with a more narrow bezel, the space allowed for clock signal lines becomes smaller, and thus RC delay in the clock signal lines undesirably increases.